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features ? mpeg i/ii-layer 3 hardwired decoder ? stand-alone mp3 decoder ? 48, 44.1, 32, 24, 22.05, 16 khz sampling frequency ? separated digital volume control on left and right channels (software control using 31 steps) ? bass, medium, and treble control (31 steps) ? bass boost sound effect ? ancillary data extraction ? crc error and mpeg frame synchronization indicators ? programmable audio output for interfacing with common audio dac ? pcm format compatible ?i 2 s format compatible ? 8-bit mcu c51 core based (f max = 20 mhz) ? 2304 bytes of internal ram ? 64k bytes of code memory ? at89c51snd1c: flash (100k erase/write cycles) ? at83snd1c: rom ? 4k bytes of boot flash memory (at89c51snd1c) ? isp: download from usb (standard) or uart (option) ? external code memory ? at80c51snd1c: romless ? usb rev 1.1 controller ? full speed data transmission ? built-in pll ? mp3 audio clocks ?usb clock ? multimedia card ? interface compatibility ? atmel dataflash ? spi interface compatibility ? ide/atapi interface ? 2 channels 10-bit adc, 8 khz (8-true bit) ? battery voltage monitoring ? voice recording controlled by software ? up to 44 bits of general-purpose i/os ? 4-bit interrupt keyboard port for a 4 x n matrix ?smartmedia ? software interface ? 2 standard 16-bit timers/counters ? hardware watchdog timer ? standard full duplex uart with baud rate generator ? two wire master and slave modes controller ? spi master and slave modes controller ? power management ? power-on reset ? software programmable mcu clock ? idle mode, power-down mode ? operating conditions: ?3v, 10%, 25 ma typical operating at 25c ? temperature range: -40 c to +85 c ? packages ? tqfp80, bga81, plcc84 (development board) ?dice single-chip flash microcontroller with mp3 decoder and human interface at83snd1c at89c51snd1c at80c51snd1c 4109js?8051?10/06
2 4109js?8051?10/06 at8xc51snd1c 1. description the at8xc51snd1c are fully integrated stand-alone hardwired mpeg i/ii-layer 3 decoder with a c51 microcontroller core handling data flow and mp3-player control. the at89c51snd1c includes 64k bytes of flash memory and allows in-system programming through an embedded 4k bytes of boot flash memory. the at83snd1c includes 64k bytes of rom memory. the at80c51snd1c does not include any code memory. the at8xc51snd1c include 2304 bytes of ram memory. the at8xc51snd1c provides the necessary features for human interface like timers, keyboard port, serial or parallel interface (usb, twi, spi, ide), adc input, i 2 s output, and all external memory interface (nand or nor flash, smartmedia, multimedia, dataflash cards). 2. typical applications ?mp3-player ? pda, camera, mobile phone mp3 ? car audio/multimedia mp3 ? home audio/multimedia mp3 3. block diagram figure 3-1. at8xc51snd1c block diagram 8-bit internal bus clock and pll unit c51 (x2 core) ram 2304 bytes flash rom interrupt handler unit filt x2 x1 mp3 decoder unit twi controller mmc interface i/o scl sda mdat p0-p5 10-bit a to d converter vss vdd keyboard interface kin3:0 i 2 s/pcm audio interface avss avdd 1 alternate function of port 1 ain1:0 ports int0 int1 mosi miso 3 alternate function of port 3 4 alternate function of port 4 timers 0/1 t1 t0 spi/dataflash controller mclk mcmd sck rst aref dsel dclk sclk dout 64 kbytes usb controller d+ d- uart rxd txd ide interface ss watchdog flash boot 4 kbytes isp uvss uvdd and brg ale 33 33 3 3444411 1
3 4109js?8051?10/06 at8xc51snd1c 4. pin description 4.1 pinouts figure 4-1. at8xc51snd1c 80-pin qfp package notes: 1. isp pin is only available in at89c51snd1c product. do not connect this pin on at83snd1c product. 2. psen pin is only available in at80c51snd1c product. at89c51snd1c-ro (flash) at83snd1c-ro (rom) at80c51snd1c-ro (romless) p0.3/ad3 p0.4/ad4 p0.5/ad5 vss vdd p0.6/ad6 p0.7/ad7 p2.0/a8 p2.1/a9 p3.1/txd p3.2/int0 p3.3/int1 p3.4/t0 p3.0/rxd 1 2 3 4 5 6 7 8 13 11 10 p2.2/a1 0 p2.3/a1 1 p2.4/a1 2 p2.6/a1 4 p2.5/a1 3 p2.7/a1 5 mclk mdat mcmd p0.2/ad2 p0.1/ad1 p0.0/ad0 pvss vss x2 x1 tst vss 9 12 14 15 16 p4.3/ss p4.2/sck p4.1/mosi p4.0/miso vss vdd rst sclk dsel dclk dout ain1 ain0 arefn arefp avss avdd p3.7/rd p3.6/wr p3.5/t1 vdd p1.0/kin0 p1.1/kin1 p1.2/kin2 p1.3/kin3 p1.4 p1.5 p1.7/sda filt pvdd vdd p1.6/scl 17 18 19 20 21 22 23 24 25 26 27 28 33 31 30 29 32 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 53 51 50 49 52 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 73 71 70 69 72 74 75 76 77 78 79 80 ale isp 1 /psen 2 /nc uvdd uvss p5.0 p5.1 p4.7 p4.6 d- d+ p5.3 p5.2 vss vdd p4.5 p4.4
4 4109js?8051?10/06 at8xc51snd1c figure 4-2. at8xc51snd1c 81-pin bga package notes: 1. isp pin is only available in at89c51snd1c product. do not connect this pin on at83snd1c and at80c51snd1c product. 2. psen pin is only available in at80c51snd1c product. p5.0 8 9765432 c b a d e f g h 1 ale p1.1 p1.4 vdd x2 vss uvdd d+ isp 1 / p1.5 x1 pvss tst d- vss p0.0/ p1.0/ p1.7/ pvdd uvss vdd p3.1/ p3.0/ p0.2/ p5.1 p1.6/ filt p3.4/ p3.5/ p3.3/ p3.2/ vdd p0.1/ vss p0.5/ avdd p3.7/ ain0 p3.6/ p4.2/ p4.3/ p0.6 p0.7/ p2.7/ mdat p5.3 avss arefn p4.0/ p4.1/ p2.1/ p4.5 vss mclk dout ain1 arefp p2.0/ p4.7 p2.2/ p2.6/ p2.3/ mcmd sclk vss p5.2 p4.6 p4.4 p2.5/ p2.4/ vdd rst dsel dclk vdd j kin0 p1.3/ kin3 p1.2/ kin2 ss mosi miso sck ad2 p0.3/ ad3 a8 p0.4/ ad4 ad0 ad1 ad7 ad5 a9 a10 a12 a11 a13 a14 a15 scl sda rxd txd int0 int1 t1 t0 rd wr psen 2 nc
5 4109js?8051?10/06 at8xc51snd1c figure 4-3. at8xc51snd1c 84-pin plcc package 4.2 signals all the at8xc51snd1c signals are detailed by functionality in table 1 to table 14 . table 1. ports signal description at89c51snd1c-sr (flash) p0.3/ad3 p0.4/ad4 p0.5/ad5 vss vdd p0.6/ad6 p0.7/ad7 p2.0/a8 p2.1/a9 p3.3/int1 p3.4/t0 p3.5/t1 p3.6/wr p3.2/int0 65 64 63 62 61 60 59 58 55 56 57 12 13 14 15 16 17 22 20 19 33 34 35 36 37 4 3 2 1 84 83 82 81 80 79 78 nc p2.3/a11 p2.4/a12 p2.6/a14 p2.5/a13 p2.7/a15 mclk mdat mcmd p0.2/ad2 p0.1/ad1 p5.0 pavss vss x2 nc x1 p3.1/txd 18 21 23 24 25 38 39 40 41 42 69 68 67 66 70 5 6 7 8 9 p4.3/ss p4.2/sck p4.1/mosi p4.0/miso vss vdd rst sclk dsel dclk dout ain1 ain0 arefn arefp avss avdd vss vdd p3.7/rd p3.0/rxd p1.0/kin0 p1.1/kin1 p1.2/kin2 p1.3/kin3 p1.4 p1.5 p1.7/sda filt pavdd vdd p1.6/scl 26 43 tst p5.2 p0.0/ad0 77 p2.2/a10 54 ale isp nc p5.1 p4.7 p4.6 76 75 10 11 28 27 29 30 31 32 uvdd uvss 44 45 46 47 48 49 50 51 52 53 74 73 72 71 p4.4 p4.5 vdd vss d- d+ nc p5.3 signal name type description alternate function p0.7:0 i/o port 0 p0 is an 8-bit open-drain bidirectional i/o port. port 0 pins that have 1s written to them float and can be used as high impedance inputs. to avoid any parasitic current consumption, floating p0 inputs must be polarized to v dd or v ss . ad7:0 p1.7:0 i/o port 1 p1 is an 8-bit bidirectional i/o port with internal pull-ups. kin3:0 scl sda p2.7:0 i/o port 2 p2 is an 8-bit bidirectional i/o port with internal pull-ups. a15:8
6 4109js?8051?10/06 at8xc51snd1c table 2. clock signal description table 3. timer 0 and timer 1 signal description p3.7:0 i/o port 3 p3 is an 8-bit bidirectional i/o port with internal pull-ups. rxd txd int0 int1 t0 t1 wr rd p4.7:0 i/o port 4 p4 is an 8-bit bidirectional i/o port with internal pull-ups. miso mosi sck ss p5.3:0 i/o port 5 p5 is a 4-bit bidirectional i/o port with internal pull-ups. - signal name type description alternate function x1 i input to the on-chip inverting oscillator amplifier to use the internal oscillator, a crys tal/resonator circuit is connected to this pin. if an external oscillator is used, its output is connected to this pin. x1 is the clock source for internal timing. - x2 o output of the on-chip inverting oscillator amplifier to use the internal oscillator, a crys tal/resonator circuit is connected to this pin. if an external oscillator is used, leave x2 unconnected. - filt i pll low pass filter input filt receives the rc network of the pll low pass filter. - signal name type description alternate function int0 i timer 0 gate input int0 serves as external run contro l for timer 0, when selected by gate0 bit in tcon register. external interrupt 0 int0 input sets ie0 in the tcon register. if bit it0 in this register is set, bit ie0 is set by a falling edge on int0 . if bit it0 is cleared, bit ie0 is set by a low level on int0 . p3.2 int1 i timer 1 gate input int1 serves as external run contro l for timer 1, when selected by gate1 bit in tcon register. external interrupt 1 int1 input sets ie1 in the tcon register. if bit it1 in this register is set, bit ie1 is set by a falling edge on int1 . if bit it1 is cleared, bit ie1 is set by a low level on int1 . p3.3 signal name type description alternate function
7 4109js?8051?10/06 at8xc51snd1c table 4. audio interface signal description table 5. usb controller signal description table 6. mutimediacard interface signal description t0 i timer 0 external clock input when timer 0 operates as a counter, a falling edge on the t0 pin increments the count. p3.4 t1 i timer 1 external clock input when timer 1 operates as a counter, a falling edge on the t1 pin increments the count. p3.5 signal name type description alternate function dclk o dac data bit clock - dout o dac audio data - dsel o dac channel select signal dsel is the sample rate clock output. - sclk o dac system clock sclk is the oversampling clock synchronized to the digital audio data (dout) and the channel selection signal (dsel). - signal name type description alternate function d+ i/o usb positive data upstream port this pin requires an external 1.5 k pull-up to v dd for full speed operation. - d- i/o usb negative data upstream port - signal name type description alternate function mclk o mmc clock output data or command clock transfer. - mcmd i/o mmc command line bidirectional command channel used for card initialization and data transfer commands. to avoid any parasitic current consumption, unused mcmd input must be polarized to v dd or v ss . - mdat i/o mmc data line bidirectional data channel. to avoid any parasitic current consumption, unused mdat input must be polarized to v dd or v ss . - signal name type description alternate function
8 4109js?8051?10/06 at8xc51snd1c table 7. uart signal description table 8. spi controller signal description table 9. twi controller signal description table 10. a/d converter signal description signal name type description alternate function rxd i/o receive serial data rxd sends and receives data in serial i/o mode 0 and receives data in serial i/o modes 1, 2 and 3. p3.0 txd o transmit serial data txd outputs the shift clock in serial i/o mode 0 and transmits data in serial i/o modes 1, 2 and 3. p3.1 signal name type description alternate function miso i/o spi master input slave output data line when in master mode, miso receives data from the slave peripheral. when in slave mode, miso outputs data to the master controller. p4.0 mosi i/o spi master output slave input data line when in master mode, mosi outputs data to the slave peripheral. when in slave mode, mosi receives data from the master controller. p4.1 sck i/o spi clock line when in master mode, sck outputs clock to the slave peripheral. when in slave mode, sck receives clock from the master controller. p4.2 ss i spi slave select line when in controlled slave mode, ss enables the slave mode. p4.3 signal name type description alternate function scl i/o twi serial clock when twi controller is in master mode, scl outputs the serial clock to the slave peripherals. when twi controller is in slave mode, scl receives clock from the master controller. p1.6 sda i/o twi serial data sda is the bidirectional two wire data line. p1.7 signal name type description alternate function ain1:0 i a/d converter analog inputs - arefp i analog positive voltage reference input - arefn i analog negative voltage reference input this pin is internally connected to avss. -
9 4109js?8051?10/06 at8xc51snd1c table 11. keypad interface signal description table 12. external access signal description notes: 1. for rom/flash dice product versions: pad ea must be connected to vcc. 2. for romless dice product versions: pad ea must be connected to vss. table 13. system signal description signal name type description alternate function kin3:0 i keypad input lines holding one of these pins high or low for 24 oscillator periods triggers a keypad interrupt. p1.3:0 signal name type description alternate function a15:8 i/o address lines upper address lines for the external bus. multiplexed higher address and data lines for the ide interface. p2.7:0 ad7:0 i/o address/data lines multiplexed lower address and data lines for the external memory or the ide interface. p0.7:0 ale o address latch enable output ale signals the start of an external bus cycle and indicates that valid address information is available on lines a7:0. an external latch is used to demultiplex the address from address/data bus. - psen i/o program store enable output (at80c51snd1c only) this signal is active low during ex ternal code fetch or external code read (movc instruction). - isp i/o isp enable input (at89c51snd1c only) this signal must be held to gnd through a pull-down resistor at the falling reset to force execution of the internal bootloader. - rd o read signal read signal asserted during external data memory read operation. p3.7 wr o write signal write signal asserted during external data memory write operation. p3.6 ea (1)(2) i external access enable (dice only) ea must be externally held low to enable the device to fetch code from external program memory locations 0000h to ffffh. - signal name type description alternate function rst i reset input holding this pin high for 64 oscillator periods while the oscillator is running resets the device. the port pins are driven to their reset conditions when a voltage lower than v il is applied, whether or not the oscillator is running. this pin has an internal pull-down re sistor which allows the device to be reset by connecting a capacitor between this pin and v dd . asserting rst when the chip is in idle mode or power-down mode returns the chip to normal operation. - tst i test input test mode entry signal. this pin must be set to v dd . -
10 4109js?8051?10/06 at8xc51snd1c table 14. power signal description signal name type description alternate function vdd pwr digital supply voltage connect these pins to +3v supply voltage. - vss gnd circuit ground connect these pins to ground. - avdd pwr analog supply voltage connect this pin to +3v supply voltage. - avss gnd analog ground connect this pin to ground. - pvdd pwr pll supply voltage connect this pin to +3v supply voltage. - pvss gnd pll circuit ground connect this pin to ground. - uvdd pwr usb supply voltage connect this pin to +3v supply voltage. - uvss gnd usb ground connect this pin to ground. -
11 4109js?8051?10/06 at8xc51snd1c 4.3 internal pin structure table 15. detailed internal pin structure notes: 1. for information on resistors value, input/output levels, and drive capability, refer to the section ?dc characteristics?, page 180 . 2. when the two wire controller is enabled, p 1 , p 2 , and p 3 transistors are disabled allowing pseudo open-drain structure. 3. in port 2, p 1 transistor is continuously driven when outputting a high level bit address (a15:8). circuit (1) type pins input tst input/output rst input/output p1 (2) p2 (3) p3 p4 p53:0 input/output p0 mcmd mdat isp psen output ale sclk dclk dout dsel mclk input/output d+ d- r tst vdd r rst vss p vdd watchdog output p 3 vss n p 1 vdd vdd 2 osc latch output periods p 2 vdd vss n p vdd vss n p vdd d+ d-
12 4109js?8051?10/06 at8xc51snd1c 5. application information figure 5-1. at8xc51snd1c typical application with on-board atmel dataflash and 2-wire lcd ref. battery dout dclk dsel sclk p1.4 p1.5 ain0 mclk x1 x2 vss avss vrefp vrefn vdd avdd ain1 mdat mcmd mmc1 mmc2 audio dac rst lcd p1.7/sda p1.6/scl p1.1/kin1 p0.0 p0.1 p1.2/kin2 p1.3/kin3 p0.2 p0.3 p1.0/kin0 filt pvss dataflash p4.2/sck p4.0/si p4.1/so memories p4n at8xc51snd1c usb port d+ d- uvdd uvss
13 4109js?8051?10/06 at8xc51snd1c figure 5-2. at8xc51snd1c typical application with on-board atmel dataflash and // lcd figure 5-3. at8xc51snd1c typical application with on-board ssfdc flash ref. battery dataflash dout dclk dsel sclk p1.4 p1.5 ain0 mclk x1 x2 vss avss vrefp vrefn vdd avdd ain1 mdat mcmd p4.2/sck p4.0/si p4.1/so mmc1 mmc2 audio dac rst p1.3 p1.0/kin0 p0.0 p0.1 p1.1/kin1 p1.2/kin2 p0.2 p0.3 p0.4 p0.5 p0.6 p0.7 lcd p1.7/sda p1.6/scl filt pvss memories p4.n at8xc51snd1c usb port d+ d- uvdd uvss ref. battery usb port smartmedia ssfdc memories or smartmedia cards dout dclk dsel sclk p3.4 p3.5 ain0 d+ mclk x1 x2 vss avss vrefp vrefn vdd avdd ain1 mdat mcmd p3.6/wr# p3.7/rd# mmc1 mmc2 audio dac rst d- p1.1/kin1 p0.0 p0.1 p1.2/kin2 p1.3/kin3 p0.2 p0.3 p1.0/kin0 filt pvss at8xc51snd1c p2 p0 p4.2 p4.4 p4.5 p4.6 p4.7 lcd p4.0 p4.1 uvdd uvss
14 4109js?8051?10/06 at8xc51snd1c figure 5-4. at8xc51snd1c typical application with ide cd-rom drive ref. battery ide cd-rom dout dclk dsel sclk p3.4 p3.5 ain0 mclk x1 x2 vss avss vrefp vrefn vdd avdd ain1 mdat mcmd mmc1 mmc2 audio dac rst p4.2 p1.0/kin0 p0.0 p0.1 p1.1/kin1 p1.2/kin2 p0.2 p0.3 p4.4 p4.5 p4.6 p4.7 lcd p1.7/sda p1.6/scl filt pvss at8xc51snd1c p3.6/wr# p3.7/rd# p2 p0 p4.0 p4.1 usb port d+ d- uvdd uvss
15 at8xc51snd1c 4109js?8051?10/06 1. peripherals the at8xc51snd1c peripherals are briefly described in the following sections. for fur- ther details on how to interface (hardware and software) to these peripherals, please refer to the at8xc51snd1c design guide. 1.1 clock generator system the at8xc51snd1c internal clocks are extracted from an on-chip pll fed by an on- chip oscillator. four clocks are generated respectively for the c51 core, the mp3 decoder, the audio interface, and the other peripherals. the c51 and peripheral clocks are derived from the oscillator clock. t he mp3 decoder clock is generated by dividing the pll output clock. the audio interface sample rates are also obtained by dividing the pll output clock. 1.2 ports the at8xc51snd1c implements five 8-bit ports (p0 to p4) and one 4-bit port (p5). in addition to performing general-purpose i/o, some ports are capable of external data memory operations; others allow for alternate functions. all i/o ports are bidirectional. each port contains a latch, an output driver and an input buffer. port 0 and port 2 output drivers and input buffers facilitate external memory operations. some port 1, port 3 and port 4 pins serve for both general-purpose i/o and alternate functions. 1.3 timers/counters the at8xc51snd1c implements the two general-purpose, 16-bit timers/counters of a standard c51. they are identified as timer 0, timer 1, and can independently be config- ured each to operate in a variety of modes as a timer or as an event counter. when operating as a timer, a timer/counter runs for a programmed length of time, then issues an interrupt request. when operating as a counter, a timer/counter counts neg- ative transitions on an external pin. after a preset number of counts, the counter issues an interrupt request. 1.4 watchdog timer the at8xc51snd1c implements a hardware watchdog timer that automatically resets the chip if it is allowed to time out. the wdt provides a means of recovering from rou- tines that do not complete successfully due to software or hardware malfunctions. 1.5 mp3 decoder the at8xc51snd1c implements a mpeg i/ii audio layer 3 decoder (known as mp3 decoder). in mpeg i (iso 11172-3) three layers of compression have been standardized support- ing three sampling frequencies: 48, 44.1, and 32 khz. among these layers, layer 3 allows highest compression rate of about 12:1 while still maintaining cd audio quality. for example, 3 minutes of cd audio (16-bit pcm, 44.1 khz) data, which needs about 32 mbytes of storage, can be encoded into only 2.7 mbytes of mpeg i audio layer 3 data. in mpeg ii (iso 13818-3), three additional sampling frequencies: 24, 22.05, and 16 khz are supported for low bit rates applications. the at8xc51snd1c can decode in real-time the mpeg i audio layer 3 encoded data into a pcm audio data, and also supports mpeg ii audio layer 3 additional frequencies.
16 at8xc51snd1c 4109js?8051?10/06 additional features are supported by the at8xc51snd1c mp3 decoder such as vol- ume, bass, medium, and treble controls, bass boost effect and ancillary data extraction. 1.6 audio output interface the at8xc51snd1c implements an audio output interface allowing the decoded audio bitstream to be output in various formats. it is compatible with right and left justification pcm and i 2 s formats and thanks to the on-chip pll (see section 1.1) allows connection of almost all of the commercial audio dac families available on the market. 1.7 universal serial bus interface the at8xc51snd1c implements a full speed universal serial bus interface. it can be used for the following purposes: ? download of mp3 encoded audio files by supporting the usb mass storage class. ? in system programming by supporting the usb firmware upgrade class. 1.8 multimediaca rd interface the at8xc51snd1c implements a multimediacard (mmc) interface compliant to the v2.2 specification in multimediacard mode. the mmc allows storage of mp3 encoded audio files in removable flash memory cards that can be easily plugged or removed from the application. it can also be used for in system programming. 1.9 ide/atapi interface the at8xc51snd1c provides an ide/atapi interface allowing connexion of devices such as cd-rom reader, compactflash cards, hard disk drive? it consists in a 16-bit bidirectional bus part of the low-level ansi ata/atapi specification. it is provided for mass storage interface but could be used for in system programming using cd-rom. 1.10 serial i/o interface the at8xc51snd1c implements a serial port with its own baud rate generator provid- ing one single synchronous communication mode and three full-duplex universal asynchronous receiver transmitter (uart) communication modes. it is provided for the following purposes: ? in system programming. ? remote control of the at8xc51snd1c by a host. 1.11 serial peripheral interface the at8xc51snd1c implements a serial peripheral interface (spi) supporting master and slave modes. it is provided for the following purposes: ? interfacing dataflash memory for mp3 encoded audio files storage. ? remote control of the at8xc51snd1c by a host. ? in system programming.
17 at8xc51snd1c 4109js?8051?10/06 1.12 2-wire controller the at8xc51snd1c implements a 2-wire controller supporting the four standard mas- ter and slave modes with multimaster capability. it is provided for the following purposes: ? connection of slave devices like lcd controller, audio dac? ? remote control of the at8xc51snd1c by a host. ? in system programming. 1.13 a/d controller the at8xc51snd1c implements a 2-channel 10-bit (8 true bits) analog to digital con- verter (adc). it is provided for the following purposes: ? battery monitoring. ? voice recording. ? corded remote control. 1.14 keyboard interface the at8xc51snd1c implements a keyboard interface allowing connection of 4 x n matrix keyboard. it is based on 4 inputs with programmable interrupt capability on both high or low level. these inputs are available as alternate function of p1.3:0 and allow exit from idle and power down modes.
180 4109js?8051?10/06 at8xc51snd1c 22. electrical characteristics 22.1 absolute maximum rating 22.2 dc characteristics 22.2.1 digital logic storage temperature ......................................... -65 to +150 c voltage on any other pin to v ss .................................... -0.3 to +4.0 v i ol per i/o pin ................................................................. 5 ma power dissipation ............................................................. 1 w operating conditions ambient temperature under bias........................ -40 to +85 c v dd ........................................................................................................................ 4.0v *notice: stressing the device beyond the ?absolute maxi- mum ratings? may cause permanent damage. these are stress ratings only. operation beyond the ?operating conditions? is not recommended and extended exposure beyond the ?operating conditions? may affect device reliability. table 143. digital dc characteristics v dd = 2.7 to 3.3 v, t a = -40 to +85 c symbol parameter min typ (1) max units test conditions v il input low voltage -0.5 0.2v dd - 0.1 v v ih1 (2) input high voltage (except rst, x1) 0.2v dd + 1.1 v dd v v ih2 input high voltage (rst, x1) 0.7v dd v dd + 0.5 v v ol1 output low voltage (except p0, ale, mcmd, mdat, mclk, sclk, dclk, dsel, dout) 0.45 v i ol = 1.6 ma v ol2 output low voltage (p0, ale, mcmd, mdat, mclk, sclk, dclk, dsel, dout) 0.45 v i ol = 3.2 ma v oh1 output high voltage (p1, p2, p3, p4 and p5) v dd - 0.7 v i oh = -30 a v oh2 output high voltage (p0, p2 address mode, ale, mcmd, mdat, mclk, sclk, dclk, dsel, dout, d+, d-) v dd - 0.7 v i oh = -3.2 ma i il logical 0 input current (p1, p2, p3, p4 and p5) -50 av in = 0.45 v i li input leakage current (p0, ale, mcmd, mdat, mclk, sclk, dclk, dsel, dout) 10 a 0.45< v in < v dd i tl logical 1 to 0 transition current (p1, p2, p3, p4 and p5) -650 av in = 2.0 v r rst pull-down resistor 50 90 200 k c io pin capacitance 10 pf t a = 25 c v ret v dd data retention limit 1.8 v
181 4109js?8051?10/06 at8xc51snd1c notes: 1. typical values are obtained using v dd = 3 v and t a = 25 c. they are not tested and there is no guarantee on these values. 2. flash retention is guaranteed with the same formula for v dd min down to 0v. 3. see tab l e 144 for typical consumption in player mode. table 144. typical reference design at89c51snd1c power consumption i dd at89c51snd1c operating current (3) x1 / x2 mode 6.5 / 10.5 8 / 13.5 9.5 / 17 ma v dd < 3.3 v 12 mhz 16 mhz 20 mhz at83snd1c operating current x1 / x2 mode 6.5 / 10.5 8 / 13.5 9.5 / 17 ma v dd < 3.3 v 12 mhz 16 mhz 20 mhz at80c51snd1c idle mode current x1 / x2 mode 6.5 / 10.5 8 / 13.5 9.5 / 17 ma v dd < 3.3 v 12 mhz 16 mhz 20 mhz i dl at89c51snd1c idle mode current (3) x1 / x2 mode 5.3 / 8.1 6.4 / 10.3 7.5 / 13 ma v dd < 3.3 v 12 mhz 16 mhz 20 mhz at83snd1c idle mode current x1 / x2 mode 5.3 / 8.1 6.4 / 10.3 7.5 / 13 ma v dd < 3.3 v 12 mhz 16 mhz 20 mhz at80c51snd1c idle mode current x1 / x2 mode 5.3 / 8.1 6.4 / 10.3 7.5 / 13 ma v dd < 3.3 v 12 mhz 16 mhz 20 mhz i pd at89c51snd1c power-down mode current 20 500 av ret < v dd < 3.3 v at83snd1c power-down mode current 20 500 av ret < v dd < 3.3 v at80c51snd1c power-down mode current 20 500 av ret < v dd < 3.3 v i fp at89c51snd1c flash programming current 15 ma v dd < 3.3 v table 143. digital dc characteristics v dd = 2.7 to 3.3 v, t a = -40 to +85 c symbol parameter min typ (1) max units test conditions player mode i dd test conditions stop 10 ma at89c51snd1c at 16 mhz, x2 mode, v dd = 3 v no song playing playing 30 ma at89c51snd1c at 16 mhz, x2 mode, v dd = 3 v mp3 song with fs= 44.1 khz, at any bit rates (variable bit rate)
182 4109js?8051?10/06 at8xc51snd1c 22.2.1.1 i dd, i dl and i pd test con ditio ns figure 22-1. i dd test condition, active mode figure 22-2. i dl test condition, idle mode figure 22-3. i pd test condition, power-down mode rst tst p0 all other pins are unconnected vdd vdd vdd i dd vdd pvdd uvdd avdd x2 clock signal vss x1 (nc) vss pvss uvss avss x2 vdd clock signal rst vss tst x1 p0 (nc) i dl all other pins are unconnected vss vdd vss vdd pvdd uvdd avdd pvss uvss avss rst mcmd p0 all other pins are unconnected vss vdd tst mdat vdd i pd vdd pvdd uvdd avdd x2 vss x1 (nc) vss pvss uvss avss
183 4109js?8051?10/06 at8xc51snd1c 22.2.2 a to d converter table 145. a to d converter dc characteristics v dd = 2.7 to 3.3 v, t a = -40 to +85 c 22.2.3 oscillator & crystal 22.2.3.1 schematic figure 22-4. crystal connection note: for operation with most standard crystals, no external components are needed on x1 and x2. it may be necessary to add external capacitors on x1 and x2 to ground in special cases (max 10 pf). x1 and x2 may not be used to drive other circuits. 22.2.3.2 parameters table 146. oscillator & crystal characteristics v dd = 2.7 to 3.3 v, t a = -40 to +85 c symbol parameter min typ max units test conditions av dd analog supply voltage 2.7 3.3 v ai dd analog operating supply current 600 a av dd = 3.3v ain1:0= 0 to av dd aden= 1 ai pd analog standby current 2 a av dd = 3.3v aden= 0 or pd= 1 av in analog input voltage av ss av dd v av ref reference voltage a refn a refp av ss 2.4 av dd v r ref aref input resistance 10 30 k t a = 25 c c ia analog input capacitance 10 pf t a = 25 c vss x1 x2 q c1 c2 symbol parameter min typ max unit c x1 internal capacitance (x1 - vss) 10 pf c x2 internal capacitance (x2 - vss) 10 pf c l equivalent load capacitance (x1 - x2) 5 pf dl drive level 50 w f crystal frequency 20 mhz rs crystal series resistance 40 cs crystal shunt capacitance 6 pf
184 4109js?8051?10/06 at8xc51snd1c 22.2.4 phase lock loop 22.2.4.1 schematic figure 22-5. pll filter connection 22.2.4.2 parameters table 147. pll filter characteristics v dd = 2.7 to 3.3 v, t a = -40 to +85 c 22.2.5 usb connection 22.2.5.1 schematic figure 22-6. usb connection 22.2.5.2 parameters table 148. usb characteristics v dd = 2.7 to 3.3 v, t a = -40 to +85 c vss filt r c1 c2 vss symbol parameter min typ max unit r filter resistor 100 c1 filter capacitance 1 10 nf c2 filter capacitance 2 2.2 nf d+ d- vbus gnd d+ d- vss to p o w e r r usb r usb vdd supply r fs symbol parameter min typ max unit r usb usb termination resistor 27 r fs usb full speed resistor 1.5 k
185 4109js?8051?10/06 at8xc51snd1c 22.2.6 in system programming 22.2.6.1 schematic figure 22-7. isp pull-down connection 22.2.6.2 parameters table 149. isp pull-down characteristics v dd = 2.7 to 3.3 v, t a = -40 to +85 c vss isp r isp symbol parameter min typ max unit r isp isp pull-down resistor 2.2 k
186 4109js?8051?10/06 at8xc51snd1c 22.3 ac characteristics 22.3.1 external program bus cycles 22.3.1.1 definition of symbols table 150. external program bus cycles timing symbol definitions 22.3.1.2 timings test conditions: capacitive load on all pins= 50 pf. table 151. external program bus cycle - read ac timings v dd = 2.7 to 3.3 v, t a = -40 to +85 c signals conditions a address h high i instruction in l low lale vvalid ppsen x no longer valid zfloating symbol parameter variable clock standard mode variable clock x2 mode unit min max min max t clcl clock period 50 50 ns t lhll ale pulse width 2t clcl -15 t clcl -15 ns t av ll address valid to ale low t clcl -20 0.5t clcl -20 ns t llax address hold after ale low t clcl -20 0.5t clcl -20 ns t lliv ale low to valid instruction 4t clcl -35 2t clcl -35 ns t plph psen pulse width 3t clcl -25 1.5t clcl -25 ns t pliv psen low to valid instruction 3t clcl -35 1.5t clcl -35 ns t pxix instruction hold after psen high 0 0 ns t pxiz instruction float after psen high t clcl -10 0.5t clcl -10 ns t aviv address valid to valid instruction 5t clcl -35 2.5t clcl -35 ns t plaz psen low to address float 10 10 ns
187 4109js?8051?10/06 at8xc51snd1c 22.3.1.3 waveforms figure 22-8. external program bus cycle - read waveforms 22.3.2 external data 8-bit bus cycles 22.3.2.1 definition of symbols table 152. external data 8-bit bus cycles timing symbol definitions 22.3.2.2 timings test conditions: capacitive load on all pins= 50 pf. table 153. external data 8-bit bus cycle - read ac timings v dd = 2.7 to 3.3 v, t a = -40 to +85 c t pliv p2 p0 psen ale t lhll t plph instruction in a15:8 t llpl a7:0 a15:8 t avll t llax t plaz d7:0 t pxix t pxiz d7:0 t pxav instruction in a7:0 d7:0 signals conditions a address h high d data in l low lale vvalid q data out x no longer valid rrd zfloating wwr symbol parameter variable clock standard mode variable clock x2 mode unit min max min max t clcl clock period 50 50 ns t lhll ale pulse width 2t clcl -15 t clcl -15 ns t avll address valid to ale low t clcl -20 0.5t clcl -20 ns t llax address hold after ale low t clcl -20 0.5t clcl -20 ns t llrl ale low to rd low 3t clcl -30 1.5t clcl -30 ns
188 4109js?8051?10/06 at8xc51snd1c table 154. external data 8-bit bus cycle - write ac timings v dd = 2.7 to 3.3 v, t a = -40 to +85 c t rlrh rd pulse width 6t clcl -25 3t clcl -25 ns t rhlh rd high to ale high t clcl -20 t clcl +20 0.5t clcl -20 0.5t clcl +20 ns t av dv address valid to valid data in 9t clcl -65 4.5t clcl -65 ns t avrl address valid to rd low 4t clcl -30 2t clcl -30 ns t rldv rd low to valid data 5t clcl -30 2.5t clcl -30 ns t rlaz rd low to address float 0 0 ns t rhdx data hold after rd high 0 0 ns t rhdz data float after rd high 2t clcl -25 t clcl -25 ns symbol parameter variable clock standard mode variable clock x2 mode unit min max min max t clcl clock period 50 50 ns t lhll ale pulse width 2t clcl -15 t clcl -15 ns t avll address valid to ale low t clcl -20 0.5t clcl -20 ns t llax address hold after ale low t clcl -20 0.5t clcl -20 ns t llwl ale low to wr low 3t clcl -30 1.5t clcl -30 ns t wlwh wr pulse width 6t clcl -25 3t clcl -25 ns t whlh wr high to ale high t clcl -20 t clcl +20 0.5t clcl -20 0.5t clcl +20 ns t avwl address valid to wr low 4t clcl -30 2t clcl -30 ns t qvwh data valid to wr high 7t clcl -20 3.5t clcl -20 ns t whqx data hold after wr high t clcl -15 0.5t clcl -15 ns symbol parameter variable clock standard mode variable clock x2 mode unit min max min max
189 4109js?8051?10/06 at8xc51snd1c 22.3.2.3 waveforms figure 22-9. external data 8-bit bus cycle - read waveforms figure 22-10. external data 8-bit bus cycle - write waveforms 22.3.3 external ide 16-bit bus cycles 22.3.3.1 definition of symbols table 155. external ide 16-bit bus cycles timing symbol definitions t avdv t llax t rhdx t rhdz t avll t avrl p2 p0 rd ale t lhll t rlrh data in a15:8 t rlaz t llrl t rhlh t rldv d7:0 a7:0 t whlh t av wl t llax t whqx p2 p0 wr ale t lhll t wlwh a15:8 t avll t qvwh d7:0 data out t llwl a7:0 signals conditions a address h high d data in l low lale vvalid q data out x no longer valid rrd zfloating wwr
190 4109js?8051?10/06 at8xc51snd1c 22.3.3.2 timings test conditions: capacitive load on all pins= 50 pf. table 156. external ide 16-bit bus cycle - data read ac timings v dd = 2.7 to 3.3 v, t a = -40 to +85 c table 157. external ide 16-bit bus cycle - data write ac timings v dd = 2.7 to 3.3 v, t a = -40 to +85 c symbol parameter variable clock standard mode variable clock x2 mode unit min max min max t clcl clock period 50 50 ns t lhll ale pulse width 2t clcl -15 t clcl -15 ns t avll address valid to ale low t clcl -20 0.5t clcl -20 ns t llax address hold after ale low t clcl -20 0.5t clcl -20 ns t llrl ale low to rd low 3t clcl -30 1.5t clcl -30 ns t rlrh rd pulse width 6t clcl -25 3t clcl -25 ns t rhlh rd high to ale high t clcl -20 t clcl +20 0.5t clcl -20 0.5t clcl +20 ns t av dv address valid to valid data in 9t clcl -65 4.5t clcl -65 ns t avrl address valid to rd low 4t clcl -30 2t clcl -30 ns t rldv rd low to valid data 5t clcl -30 2.5t clcl -30 ns t rlaz rd low to address float 0 0 ns t rhdx data hold after rd high 0 0 ns t rhdz data float after rd high 2t clcl -25 t clcl -25 ns symbol parameter variable clock standard mode variable clock x2 mode unit min max min max t clcl clock period 50 50 ns t lhll ale pulse width 2t clcl -15 t clcl -15 ns t avll address valid to ale low t clcl -20 0.5t clcl -20 ns t llax address hold after ale low t clcl -20 0.5t clcl -20 ns t llwl ale low to wr low 3t clcl -30 1.5t clcl -30 ns t wlwh wr pulse width 6t clcl -25 3t clcl -25 ns t whlh wr high to ale high t clcl -20 t clcl +20 0.5t clcl -20 0.5t clcl +20 ns t avwl address valid to wr low 4t clcl -30 2t clcl -30 ns t qvwh data valid to wr high 7t clcl -20 3.5t clcl -20 ns t whqx data hold after wr high t clcl -15 0.5t clcl -15 ns
191 4109js?8051?10/06 at8xc51snd1c 22.3.3.3 waveforms figure 22-11. external ide 16-bit bus cycle - data read waveforms note: 1. d15:8 is written in dat16h sfr. figure 22-12. external ide 16-bit bus cycle - data write waveforms note: 1. d15:8 is the content of dat16h sfr. 22.4 spi interface 22.4.0.4 definition of symbols table 158. spi interface timing symbol definitions t avdv t llax t rhdx t rhdz t avll t avrl p2 p0 rd ale t lhll t rlrh data in t rlaz t llrl t rhlh t rldv d7:0 a7:0 data in d15:8 (1) a15:8 t whlh t av wl t llax t whqx p2 p0 wr ale t lhll t wlwh t avll t qvwh d7:0 data out t llwl a7:0 d15:8 (1) data out a15:8 signals conditions c clock h high i data in l low o data out v valid x no longer valid zfloating
192 4109js?8051?10/06 at8xc51snd1c 22.4.0.5 timings test conditions: capacitive load on all pins= 50 pf. table 159. spi interface master ac timing v dd = 2.7 to 3.3 v, t a = -40 to +85 c note: 1. value of this parameter depends on software. symbol parameter min max unit slave mode t chch clock period 2 t per t chcx clock high time 0.8 t per t clcx clock low time 0.8 t per t slch , t slcl ss low to clock edge 100 ns t ivcl , t ivch input data valid to clock edge 40 ns t clix , t chix input data hold after clock edge 40 ns t clov, t chov output data valid after clock edge 40 ns t clox , t chox output data hold time after clock edge 0 ns t clsh , t chsh ss high after clock edge 0 ns t slov ss low to output data valid 50 ns t shox output data hold after ss high 50 ns t shsl ss high to ss low (1) t ilih input rise time 2 s t ihil input fall time 2 s t oloh output rise time 100 ns t ohol output fall time 100 ns master mode t chch clock period 2 t per t chcx clock high time 0.8 t per t clcx clock low time 0.8 t per t ivcl , t ivch input data valid to clock edge 20 ns t clix , t chix input data hold after clock edge 20 ns t clov, t chov output data valid after clock edge 40 ns t clox , t chox output data hold time after clock edge 0 ns t ilih input data rise time 2 s t ihil input data fall time 2 s t oloh output data rise time 50 ns t ohol output data fall time 50 ns
193 4109js?8051?10/06 at8xc51snd1c 22.4.0.6 waveforms figure 22-13. spi slave waveforms (sscpha= 0) note: 1. not defined but generally the msb of the character which has just been received. figure 22-14. spi slave waveforms (sscpha= 1) note: 1. not defined but generally the lsb of the character which has just been received. t slcl t slch t chcl t clch mosi (input) sck (sscpol= 0) (input) ss (input) sck (sscpol= 1) (input) miso (output) t chch t clcx t chcx t ivcl t clix t chix t ivch t chov t clov t chox t clox msb in bit 6 lsb in slave msb out slave lsb out bit 6 t slov (1) t shox t shsl t chsh t clsh t chcl t clch mosi (input) sck (sscpol= 0) (input) ss (input) sck (sscpol= 1) (input) miso (output) t chch t clcx t chcx t ivcl t clix t chix t ivch t clov t chov t clox t chox msb in bit 6 lsb in slave msb out slave lsb out bit 6 t slov (1) t shox t shsl t chsh t clsh t slcl t slch
194 4109js?8051?10/06 at8xc51snd1c figure 22-15. spi master waveforms (sscpha= 0) note: 1. ss handled by software using general purpose port pin. figure 22-16. spi master waveforms (sscpha= 1) note: 1. ss handled by software using general purpose port pin. 22.4.1 two-wire interface 22.4.1.1 timings table 160. twi interface ac timing mosi (input) sck (sscpol= 0) (output) ss (output) sck (sscpol= 1) (output) miso (output) t chch t clcx t chcx t ivcl t clix t chix t ivch t chov t clov t chox t clox msb in bit 6 lsb in msb out port data lsb out port data bit 6 t chcl t clch mosi (input) sck (sscpol= 0) (output) ss (1) (output) sck (sscpol= 1) (output) miso (output) t chch t clcx t chcx t ivcl t clix t chix t ivch t chov t clov t chox t clox msb in bit 6 lsb in msb out port data lsb out port data bit 6 t chcl t clch
195 4109js?8051?10/06 at8xc51snd1c v dd = 2.7 to 3.3 v, t a = -40 to +85 c notes: 1. at 100 kbit/s. at other bit-rates this value is inversely proportional to the bit-rate of 100 kbit/s. 2. determined by the external bus-line capacitance and the external bus-line pull-up resistor, this must be < 1 s. 3. spikes on the sda and scl lines with a duration of less than 3t clcl will be filtered out. maxi - mum capacitance on bus-lines sda and scl= 400 pf. 4. t clcl = t osc = one oscillator clock period. 22.4.1.2 waveforms figure 22-17. two wire waveforms symbol parameter input m i n max output m i n max t hd ; sta start condition hold time 14t clcl (4) 4.0 s (1) t low scl low time 16t clcl (4) 4.7 s (1) t high scl high time 14t clcl (4) 4.0 s (1) t rc scl rise time 1 s- (2) t fc scl fall time 0.3 s0.3 s (3) t su ; dat1 data set-up time 250 ns 20t clcl (4) - t rd t su ; dat2 sda set-up time (before repeated start condition) 250 ns 1 s (1) t su ; dat3 sda set-up time (before stop condition) 250 ns 8t clcl (4) t hd ; dat data hold time 0 ns 8t clcl (4) - t fc t su ; sta repeated start set-up time 14t clcl (4) 4.7 s (1) t su ; sto stop condition set-up time 14t clcl (4) 4.0 s (1) t buf bus free time 14t clcl (4) 4.7 s (1) t rd sda rise time 1 s - (2) t fd sda fall time 0.3 s0.3 s (3) tsu ;d at 1 t su ;sta ts u ; d at 2 t hd ;sta t high t low sda (input/output) 0.3 v dd 0.7 v dd t buf t su ;sto 0.7 v dd 0.3 v dd t rd t fd t rc t fc scl (input/output) t hd; dat t su; dat3 start or repeated start condition start condition stop condition repeated start condition
196 4109js?8051?10/06 at8xc51snd1c 22.4.2 mmc interface 22.4.2.1 definition of symbols table 161. mmc interface timing symbol definitions 22.4.2.2 timings table 162. mmc interface ac timings v dd = 2.7 to 3.3 v, t a = -40 to +85 c, cl 100pf (10 cards) 22.4.2.3 waveforms figure 22-18. mmc input-output waveforms signals conditions c clock h high d data in l low o data out v valid x no longer valid symbol parameter min max unit t chch clock period 50 ns t chcx clock high time 10 ns t clcx clock low time 10 ns t clch clock rise time 10 ns t chcl clock fall time 10 ns t dvch input data valid to clock high 3 ns t chdx input data hold after clock high 3 ns t chox output data hold after clock high 5 ns t ovch output data valid to clock high 5 ns t ivch mclk mdat input t chch t clcx t chcx t chcl t clch mcmd input t chix t ovch mdat output mcmd output t chox
197 4109js?8051?10/06 at8xc51snd1c 22.4.3 audio interface 22.4.3.1 definition of symbols table 163. audio interface timing symbol definitions 22.4.3.2 timings table 164. audio interface ac timings v dd = 2.7 to 3.3 v, t a = -40 to +85 c, cl 30pf note: 1. 32-bit format with fs = 48 khz. 22.4.3.3 waveforms figure 22-19. audio interface waveforms signals conditions c clock h high o data out l low s data select v valid x no longer valid symbol parameter min max unit t chch clock period 325.5 (1) ns t chcx clock high time 30 ns t clcx clock low time 30 ns t clch clock rise time 10 ns t chcl clock fall time 10 ns t clsv clock low to select valid 10 ns t clov clock low to data valid 10 ns d clk t chch t clcx t chcx t clch t chcl dsel d dat right left t clsv t clov
198 4109js?8051?10/06 at8xc51snd1c 22.4.4 analog to digital converter 22.4.4.1 definition of symbols table 165. analog to digital converter timing symbol definitions 22.4.4.2 characteristics table 166. analog to digital converter ac characteristics v dd = 2.7 to 3.3 v, t a = -40 to +85 c notes: 1. av dd = av refp = 3.0 v, av ss = av refn = 0 v. adc is monotonic with no missing code. 2. the differential non-linearity is the difference between the actual step width and the ideal step width (see figure 22-21 ). 3. the integral non-linearity is the peak difference between the center of the actual step and the ideal transfer curve after appropriate adjustment of gain and offset errors (see figure 22-21 ). 4. the offset error is the absolute difference between the straight line which fits the actual trans - fer curve (after removing of gain error), and the straight line which fits the ideal transfer curve (see figure 22-21 ). 5. the gain error is the relative difference in percent between the straight line which fits the actual transfer curve (after removing of offset error), and the straight line which fits the ideal transfer curve (see figure 22-21 ). signals conditions c clock h high e enable (aden bit) l low s start conversion (adsst bit) symbol parameter min max unit t clcl clock period 4 s t ehsh start-up time 4 s t shsl conversion time 11t clcl s dle differential non- linearity error (1)(2) 1lsb ile integral non- linearity errorss (1)(3) 2lsb ose offset error (1)(4) 4lsb ge gain error (1)(5) 4lsb
199 4109js?8051?10/06 at8xc51snd1c 22.4.4.3 waveforms figure 22-20. analog to digital converter internal waveforms figure 22-21. analog to digital converter characteristics aden bit adsst bit t ehsh t shsl clk t clcl 1 2 3 4 5 6 7 1018 1019 1020 1021 1022 1023 1024 1 2 3 4 5 6 7 1018 1019 1020 1021 1022 1023 offset error ose code out avin offset error ose gain error ge ideal transfer curve 1 lsb (ideal) integral non-linearity (ile) differential non-linearity (dle) center of a step example of an actual transfer curve 0 0 (lsb ideal)
200 4109js?8051?10/06 at8xc51snd1c 22.4.5 flash memory 22.4.5.1 definition of symbols table 167. flash memory timing symbol definitions 22.4.5.2 timings table 168. flash memory ac timing v dd = 2.7 to 3.3 v, t a = -40 to +85 c 22.4.5.3 waveforms figure 22-22. flash memory - isp waveforms note: 1. isp must be driven through a pull-down resistor (see section ?in system programming?, page 185 ). figure 22-23. flash memory - internal busy waveforms signals conditions sisp l low rrst vvalid b fbusy flag x no longer valid symbol parameter min typ max unit t svrl input isp valid to rst edge 50 ns t rlsx input isp hold after rst edge 50 ns t bhbl flash internal busy (programming) time 10 ms n fcy number of flash write cycles 100k cycle t fdr flash data retention time 10 years rst t svrl isp (1) t rlsx fbusy bit t bhbl
201 4109js?8051?10/06 at8xc51snd1c 22.4.6 external clock drive and logic level references 22.4.6.1 definition of symbols table 169. external clock timing symbol definitions 22.4.6.2 timings external clock ac timings v dd = 2.7 to 3.3 v, t a = -40 to +85 c 22.4.6.3 waveforms figure 22-24. external clock waveform figure 22-25. ac testing input/output waveforms note: 1. during ac testing, all inputs are driven at v dd -0.5 v for a logic 1 and 0.45 v for a logic 0. 2. timing measurements are made on all outputs at v ih min for a logic 1 and v il max for a logic 0. figure 22-26. float waveforms signals conditions c clock h high l low x no longer valid symbol parameter min max unit t clcl clock period 50 ns t chcx high time 10 ns t clcx low time 10 ns t clch rise time 3 ns t chcl fall time 3 ns t cr cyclic ratio in x2 mode 40 60 % 0.45 v t clcl v dd - 0.5 v ih1 v il t chcx t clch t chcl t clcx 0.45 v v dd - 0.5 0.7 v dd 0.3 v dd v ih min v il max inputs outputs v load v oh - 0.1 v v ol + 0.1 v v load + 0.1 v v load - 0.1 v timing reference points
202 4109js?8051?10/06 at8xc51snd1c note: for timing purposes, a port pin is no longer floating when a 100 mv change from load voltage occurs and begins to float when a 100 mv change from the loading v oh /v ol level occurs with i ol /i oh = 20 ma.
203 4109js?8051?10/06 at8xc51snd1c 24. ordering information notes: 1. refers to rom code. 2. plcc84 package only available for development board. part number memory size supply voltage temperature range max frequency package (2) packing product marking at89c51snd1c-rotil 64k flash 3v industrial 40 mhz tqfp80 tray 89c51snd1c-il at89c51snd1c-7htil 64k flash 3v industrial 40 mhz bga81 tray 89c51snd1c-il at89c51snd1c-ddv 64k flash 3v industrial 40 mhz dice tray - at83snd1cxxx (1) -rotil 64k rom 3v industrial 40 mhz tqfp80 tray 89c51snd1c-il at83snd1cxxx (1) -7htil 64k rom 3v industrial 40 mhz bga81 tray 89c51snd1c-il at83snd1cxxx-ddv 64k rom 3v industrial 40 mhz dice tray - at80c51snd1c-rotil romless 3v industrial 40 mhz tqfp80 tray 89c51snd1c-il at80c51snd1c-7htil romless 3v industrial 40 mhz bga81 tray 89c51snd1c-il at80c51snd1c-ddv romless 3v industrial 40 mhz dice tray - at89c51snd1c-rotul 64k flash 3v industrial & green 40 mhz tqfp80 tray 89c51snd1c-il at89c51snd1c-7htjl 64k flash 3v industrial 40 mhz bga81 tray 89c51snd1c-il at83snd1cxxx (1) -rotul 64k rom 3v industrial & green 40 mhz tqfp80 tray 89c51snd1c-il at83snd1cxxx (1) -7htjl 64k rom 3v industrial & green 40 mhz bga81 tray 89c51snd1c-il at80c51snd1c-rotul romless 3v industrial & green 40 mhz tqfp80 tray 89c51snd1c-il AT80C51SND1C-7HTJL romless 3v industrial & green 40 mhz bga81 tray 89c51snd1c-il
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